The present invention relates to testing of complex combinatorial and sequential logic circuits embodied in large scale integration (LSI) and very large scale integration (VLSI) circuit devices.
A fault occurring anywhere in such a LSI or VLSI circuit device can have its effect propagated through a number of feedback loops including storage or memory elements in the sequential logic before reaching a testable output of the device. Level sensitive scan design (LSSD) rules were devised to eliminate the complications in testing caused by this propagation through feedback loops. As described by E. B. Eichelberger and T. W. Williams in an article entitled xe2x80x9cA Logic Design Structure for LSI Testablilityxe2x80x9d on pages 462-468 of the Proceedings of the 14th Design Automation conf., LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, test input signals can be introduced or test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD techniques include U.S. Pat. No. 3,783,254; U.S. Pat. No. 3,784,907; U.S. Pat. No. 3,961,252 and U.S. Pat. No. 4,513,418. The subject matter of these patents and the above described Eichelberger and Williams article are hereby included by reference.
As shown in FIG. 1, in accordance with LSSD rules, shift register latches (SRL""s) 100 on a semiconductor chip 102 are coupled together to form a shift register LSSD scan latch chain 104 to facilitate testing of combinational logic blocks 106, 108 and 110 interconnected by the SRLs 100 of the scan latch chain 104. While a single scan latch chain is shown here, it should be understood that what follows applies equally as well to latches arranged in multiple scan chains on the chip.
Data is inputted to the combinational logic blocks 106, 108 and 110 and the SRLs 100 in a parallel through primary inputs (PIs) 112 of the chip 102. Data is outputted from the combinational logic blocks 106, 108 and 110 and the SRLs 100 in parallel through the primary outputs (POs) vectors 114 of the chip 102. During testing, the scan chain latch circuits 104 may also be loaded serially. Serial input (SRI) 116 provides a serial input to the scan chain latch circuits 104. Similarly, serial output (SRO) 118 provides an output from scan chain latch circuits 104. Scanning inputs into the serial input SR 116 and out serial input 118 enables testing the SRLs 104 independently of the combinational logic 106, 108 and 110. It also allows each of the individual SRLs to bemused as a pseudo-primary input or a pseudo-primary output for a combinational logic block 106, 108 or 110. The logic circuits in each of the logic blocks to be tested separately of circuits in other of the logic blocks.
As shown in FIG. 2, each of the SRLs 100a to n of the LSSD scan chain 104 is actually a pair of bi-stable latches, a master latch L1 and a slave latch L2. The scan chain 104 serial input 116 is provided to SRL 100a and a serial output 118 is taken from SRL 100n. FIG. 2 shows an AND circuit or gate 202 representing a portion of the combinational logic to be tested. This AND circuit has a first input 204 connected to the output of SRL 100b, and a second input 206 connected to the output of SRL 100c. A known problem with testing using the LSSD scan chain 104 is the inability to AC test certain logic state transitions at the inputs of certain logic circuits such as AND gate 202. As shown, adjacent latches, such as 100b and 100c, feed both inputs 204 and 206 of the AND gate 202. AC coverage is always lower than DC coverage because AC tests require an initial and final state in order to define a transition. A major factor limiting AC test coverage and causing it to be much lower than DC coverage is that the required latch settings to cause a transition often conflict with the latch settings to propagate that transition. As an example, to test the illustrated 2-way AND circuit 202 for slow-to-rise faults, at least one input must have a 0xe2x86x921 transition while the other input is held at 1 or also transitions from 0 to 1. If both inputs to the AND circuit are driven by SRLs adjacent in the scan chain, those test patterns are not possible. In both cases, the 0xe2x86x921 transition on one input will cause the final state of the other input to be 0, thus blocking the transition from propagating to an observable point. This invention solves that problem and makes the propagation requirement independent of the transition requirement. In effect, a transition fault becomes just as testable as a DC stuck fault in the same location. For example, in order to test the slow-to-rise fault (0 to 1) of AND gate 202, at least one input 204 requires a 0 to 1 logic transition while input 206 requires a similar logic transition or initial and final logic states of 1. As shown by the logic 1 and 0 states of latches 208b and 210b respectively, and the 0 and 1 logic states of the latches 208c and 210c, the necessary states cannot be provided to the second input 206 because slave latch 210b and master latch 208c are directly connected and have the same 0 logic value. This latch adjacency problem can dramatically reduce the delay fault shipped product quality level (SPQL).
One suggestion for solving the latch adjacency problem is to use xe2x80x9cdummyxe2x80x9d SRLs or xe2x80x9cscan-onlyxe2x80x9d latches in between every pair of SRLs in the scan chain. This method uses more area because the dummy latches are larger than the integrated SRL complementing function. In addition, both A and B clocks must be routed to every dummy SRL. Because the number of loads increase on the A and B clocks, re-powering on those clocks generally needs to be increased.
Another major drawback of LSSD test methodology is encountered when the LSSD scan chain circuit 104 is not functioning properly and access to the internal logic of the circuit is greatly reduced. This is often the case early in the technology or product introduction cycle when the yields are relatively low or even zero. In these situations, the rapid determination of the fault""s root cause is critical, but not easily diagnosed. For example, when there is a stuck-at logic 0 fault, a serial output xe2x80x9c0xe2x80x9ds will come out of the scan chain 104 on output 118 after a certain number of clock cycles, no matter if a serial input on input 116 of mixed logic xe2x80x9c0xe2x80x9ds or xe2x80x9c1xe2x80x9ds is scanned in. From this result, it can be determined that there is a stuck-at 1 fault in the scan chain 104, but the exact SRL 100 with the fault condition cannot be located of even isolated. While several techniques have been developed in the past to diagnose this type of failure, these techniques have produced limited success.
In addition, several scan diagnostic approaches that have been proposed. Most of these test software fail data analysis approaches are based on cause-effect algorithms. In many instances, multiple test passes are required for a successful diagnostic call, while in many other cases, these approaches fail or are not very effective. Such software solutions for diagnosing the broken scan chain need more storage and simulation time. If the logic between the SRLs have faults, their diagnostic resolution is very poor. Other hardware solutions either require a large hardware overhead or offer no improvement on transition fault coverage.
The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.
Therefore, it is an object of the present invention to provide an improved circuits for use in LSSD testing.
It is another object of the invention to provide a shift register latch which will overcome the latch adjacency problem.
A further object of the present invention is to provide improved LSSD testing methods and apparatus.
A still further object of the invention is to provide a SRL in which the state of one of the latches can be complemented without affecting the state of the other of the latches.
A still further object of the invention is to provide improved stuck-at fault scan chain diagnosis.